The link provided by Barny on Feb 5 appears to provide the answer in an article by Roger Forster. The first definition is that the clock and data signals are exclusive or'ed to provide the data+clock output, and in the second case are modulo-2 added. The difference being that in the first case the data changes on the positve edge of the clock and in the second on the negative edge.
The link provided by Barny on Feb 5 appears to provide the answer in an article by Roger Forster. The first definition is that the clock and data signals are exclusive or'ed to provide the data+clock output, and in the second case are modulo-2 added. The difference being that in the first case the data changes on the positve edge of the clock and in the second on the negative edge.
