Found another insight, if I add a delay after performing the analog read, the duration of the delay affects the variation in the output. 

Maybe this is related to the effect mentioned about the adc sampling capacitors?

with a 1500 ms delay, I've reduced the adc level variation from from 6 to around 3. 

Did you mean 1500ms (so 1.5 seconds)? That's a massive delay. But yes, if you can afford a delay it always helps. I'll admit I've barely used Arduinos, but with PICs I'd always try to put in a delay of tens of milliseconds if I possibly can (there's usually a recommended delay for the number of bits of accuracy you're trying to achieve). But if you're working that slowly I'd also recommend doing a rolling average - e.g. add together the last four readings and divide by 4 (or last 8 readings and divide by 8, or last 16 readings and divide by 16 - trading time against stability). 

I thought I'd replied to your previous message but it looks like I didn't, I've been having IT issues today. Basically assuming your transducer doesn't have to have its return connection earthed at it's end (i.e. assuming it's not attached to a metal case which is earthed) then as long as the "cold" or "return" wire attaches close to the 0V connection of the ADC you should be ok irrespective of any other earths you have in your system. And as Mike says earlier, ideally run in screened cable, or next best twisted pair. 

Aaron O'Sullivan said:

I can get hold of an adaptor board to up this to 16, which should smooth out a lot of the variability I'm seeing.

Err, no...it might even appear to appear to make it worse! Let's say at the moment you're seeing a variation of 4, so two bits. With a 16 bit convertor you'll see a variation of 8 bits (so 256!) - your extra 6 bits will all be down in the noise. Actually it's no different, with a variation of 4 you have 8 stable bits now, and with a 16 bit convertor you would still have 8 stable bits. If your 10 bits was absolutely stable then moving to 16 bits would add more accuracy, down to the point where they get buried in the noise. Hope that makes sense?

By the way all this advice from Mike and myself is going to be pretty simplistic and generic - I probably have more books and other info on grounding and shielding on my bookshelves than any other single topic, it's a huge subject! But it sounds like it's a fairly straightforward application, so hopefully this should all be enough to help.

Adding more delay  is related but it is not a good way to attack it. Unless the ADC is cycling round to scan many pins in turn , the cleanest way is to camp on the one input pin, wait for the analogue settling time, then acquire, from an impedance low enough to not twitch by more than perhaps half or quarter of an LSB on the largest credible  input impedance transient.
If you do not do this the p-p variation will depend where you are on the transfer function. If you are near an MSB transition, then the load impedance step is largest, as that is the largest Cap being flicked in and out while the internal logic looks frantically  for a comparator transition.

read here, or at least stare at the first figure ;-)   Atmel are not great on explanations but their ADC method is the same as that one.
The ADCs inside Microchip  PICs are very similar. and have similar limitations on settling and conversion timings vs accuracy but only the  datasheets of the earlier devices bother to say so.

Mike.

That is a really good point about the impedance. Personally I'd put in a buffer but I'm guessing that would be a step too far.

caps are cheaper and use less power ;-)   The Atmel data sheet does not make it clear that the operation of the ADC pushes and pulls current in and out of the input pin wrt local gnd and Vref  as part of the sampling and conversion process - and the exact amount of charge on the move also depends on the residual charges left  over from the previous conversion result, which in some cases may not even have been an analogue quantity on  the same pin, and to a lesser extent  how long ago it was, as the on-chip caps leak a bit. Luckily those internal caps can only be a fraction of a pF per LSB so an external nano-farad or ten as near as poss to the chip is usually enough to make that bounce causing self interfering between readings negligibly small. (and another larger cap between Vref and ground always helps as well please. )
Note that in a modern CMOS process you cannot make large capacitors economically, even 1 or 2 pf take up the area of many hundreds of gates. So normally anything more than about 20pF needs to be off-chip.

M.