well the op-amp/ comparator  will have a reasonable power supply rejection, so the comparison decision is not going to reverse as the op amp supply varies, and I imagine you do not want a situation where the comparator inputs could ever be at a higher voltage than its power supply, or it may not survive power down, if the ESD structures on the inputs are biassed so they start to conduct into the power rails. It rather depends what that thing we assume is a 3 legged regulator is doing.

And we have to remember, it is only a pretty pattern on a mug, it may not be a circuit from any real project at all even if that is the pin out of several common op-amps.


So for  bonus points, do you fancy estimating, with or without computer simulation, at what frequency does the flip flop in this one operate?

You may assume the supply voltage is low enough that you can neglect Vbe reverse break down, and that the transistor Hfe is >>100


M.

well the op-amp/ comparator  will have a reasonable power supply rejection, so the comparison decision is not going to reverse as the op amp supply varies, and I imagine you do not want a situation where the comparator inputs could ever be at a higher voltage than its power supply, or it may not survive power down, if the ESD structures on the inputs are biassed so they start to conduct into the power rails. It rather depends what that thing we assume is a 3 legged regulator is doing.

And we have to remember, it is only a pretty pattern on a mug, it may not be a circuit from any real project at all even if that is the pin out of several common op-amps.


So for  bonus points, do you fancy estimating, with or without computer simulation, at what frequency does the flip flop in this one operate?

You may assume the supply voltage is low enough that you can neglect Vbe reverse break down, and that the transistor Hfe is >>100


M.