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RCD used for ADS on a TN system: what verifies L-N circuit impedance?

Adam Selvey

I have been looking at the implications of using an RCD to provide ADS on a TN system under Regulation 411.4.204, rather than relying on the overcurrent characteristic of the MCB/RCBO.

Historically, where the overcurrent device provides ADS, Table 41.3 gives a relatively low maximum Zs. As well as demonstrating the required earth-fault disconnection time, this also provides a useful practical check on the integrity of the installed circuit.

Where an RCD is instead relied upon for ADS, Table 41.5 can permit a dramatically higher Zs. Previous EngX discussions confirm that this is a legitimate design approach on TN systems, although several contributors have also commented that measured Zs should still be reasonable for the circuit concerned. [engx.theiet.org], [engx.theiet.org]

My question concerns verification of the line-neutral fault path.

At design stage, software such as ProDesign performs separate line and earth fault adiabatic checks. It therefore determines minimum phase fault current and verifies that the overcurrent protective device will clear an L-N fault before the conductor's thermal withstand is exceeded. Trimble describes the software as performing both line and earth fault adiabatic checks. [engx.theiet.org], [trimble.com]

However, at initial verification the principal impedance value being recorded is Zs.

Consider a TN circuit where the design calculation assumes a low L-N loop impedance, but an installation defect introduces significant resistance into the line or neutral conductor.

If the RCD is relied upon for ADS, the measured L-E Zs could remain well within the Table 41.5 limit, because very little residual current is required to operate the RCD. Yet the actual L-N fault current could now be considerably lower than that assumed in the designer's Chapter 43 calculation.

Historically, where Table 41.3 governed, there was an indirect safeguard: if the L-CPC loop, often containing a CPC smaller than the neutral, had sufficiently low impedance to operate the MCB within the required time, there was considerable confidence in the L-N fault path as well.

When Table 41.5 is used for ADS on a TN system, what verification replaces that safeguard?

More specifically:

How does initial verification demonstrate that the as-installed L-N circuit impedance remains sufficiently close to the designer's calculated value for the minimum short-circuit current and Chapter 43 thermal withstand calculation to remain valid?

I appreciate that continuity measurements provide useful information and that an unexpectedly high Zs should be investigated rather than simply accepted because it is below the RCD-derived limit. But I am struggling to identify the explicit acceptance benchmark against which the verifier assesses this where the declared maximum Zs has been derived from the RCD rather than the overcurrent device.

Am I missing another requirement in BS 7671 or Guidance Note 3 that closes this loop?

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  • 0

    An RCD doesn’t verify L–N circuit impedance directly. Its function is to detect imbalance between live and neutral currents, ensuring disconnection in case of earth leakage. For ADS in a TN system, the verification of L–N (or L–PE) impedance is normally carried out through loop impedance testing. This confirms that fault currents are high enough to operate the protective device within the required disconnection time. In practice, ADS relies on measured impedance values to validate compliance, while the RCD provides complementary protection against residual currents.

  • 0 in reply to UMAIR AHMAD

    Thanks. I understand the principles you describe, but my question is slightly different.

    I fully understand that an RCD does not verify L-N impedance and that an RCD operates on residual-current imbalance. I also understand that, on a TN system, ADS can be achieved either through the overcurrent characteristic of the protective device or, where deliberately selected by the designer, through the RCD function.

    My question is specifically about the link between design and initial verification.

    If I design a TN circuit so that the MCB or the overcurrent element of an RCBO provides ADS, I can declare the maximum permitted Zs derived from Table 41.3. That gives the verifier a meaningful limit against which the installed circuit can be assessed.

    However, if I deliberately rely on the RCD for ADS, 411.4.204 permits the Table 41.5 value to be used. The declared maximum Zs can then become orders of magnitude greater than the impedance I would reasonably expect from that TN circuit.

    So my question is:

    What meaningful design limit is the verifier expected to use to establish that the as-installed circuit impedance is consistent with the designer's assumptions when the declared maximum permitted Zs is derived from Table 41.5?

    This is particularly relevant to the L-N path. The designer may have calculated minimum prospective short-circuit current and demonstrated the thermal performance and operation of the overcurrent protective device based upon a particular circuit impedance. A high-resistance connection introduced during installation could invalidate that assumption while still leaving more than sufficient residual current to operate a 30 mA RCD.

    I am therefore not questioning whether the RCD achieves ADS. I am asking:

    Where in BS 7671 is the requirement that links the designer's calculated circuit impedance/minimum phase-fault-current assumption to an acceptance value used during initial verification? And where is that meaningful value intended to be recorded?

    The standard schedules provide a field for maximum permitted Zs, but if that value is derived from Table 41.5 it is primarily a protection limit, not necessarily a useful benchmark for determining whether a TN circuit has actually been installed with the electrical characteristics assumed by the designer.

    That is the gap I am trying to understand. If there is another regulation or verification requirement that closes that design-to-installation loop, that's specifically what I'm looking for.

  • +1 in reply to Adam Selvey

    The lack of a L-N loop impedance test is a long outstanding one ... even without RCDs. It's been a frequent comment on here that N connections appear to burn out far more often then L ones - with one possible explanation being that bad connections on L get spotted by a Zs loop test (or R1+R2 continuity test) and corrected, whereas the same initial number of bad N connections get left and so are the ones to go on to cause trouble.

    I'd agree that design should be done against the tables, but testing should be done against the design - so tests should be looking to confirm for what was expected by the design in terms of cable length/supply characteristics rather than just the BS 7671 tables. In practice, especially at the domestic end of things, a formal design process is typically skipped, so the BS 7671 tables (or the OSG 80% derivatives) are the only thing to compare test results with.

    For me the big flaw is that lack of a L-N test in the textbooks.

       - Andy.

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  • +1 in reply to Adam Selvey

    The lack of a L-N loop impedance test is a long outstanding one ... even without RCDs. It's been a frequent comment on here that N connections appear to burn out far more often then L ones - with one possible explanation being that bad connections on L get spotted by a Zs loop test (or R1+R2 continuity test) and corrected, whereas the same initial number of bad N connections get left and so are the ones to go on to cause trouble.

    I'd agree that design should be done against the tables, but testing should be done against the design - so tests should be looking to confirm for what was expected by the design in terms of cable length/supply characteristics rather than just the BS 7671 tables. In practice, especially at the domestic end of things, a formal design process is typically skipped, so the BS 7671 tables (or the OSG 80% derivatives) are the only thing to compare test results with.

    For me the big flaw is that lack of a L-N test in the textbooks.

       - Andy.

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  • 0 in reply to AJJewsbury

    Thanks, I think we're arriving at the same underlying issue, and your point about neutral connections is a really useful way of looking at it.

    I agree that the absence of an L-N loop impedance test is not something created by RCDs. A poor neutral connection can remain invisible to Zs or R1+R2 testing, whereas an equivalent resistance in the line conductor is much more likely to show up in those results.

    Where I think the RCD issue makes this particularly interesting is that it can also remove the useful benchmark we historically had for the L-PE path.

    Take a Type C RCBO. For an L-N short circuit, the residual element is irrelevant and the RCBO still has to operate on its overcurrent characteristic. For guaranteed operation in the magnetic region we are essentially back at 10 × In, which is the same characteristic underlying the Type C values in Table 41.3.

    The phase-fault adiabatic calculation can legitimately allow the fault current to fall below 10 × In because the conductor can withstand a longer clearing time. So the precise permissible L-N impedance also depends on conductor size. That calculation is perfectly valid at design stage.

    My concern is what happens to that information at verification.

    The design software has effectively established:

    Minimum permissible L-N prospective fault current, and therefore implicitly a maximum permissible L-N loop impedance, based on the cable and overcurrent protective-device characteristic.

    But that resulting impedance does not appear to be passed to the verifier or recorded on the standard test schedule.

    If the RCD is then deliberately used for ADS, the recorded maximum Zs may instead come from Table 41.5 and be orders of magnitude higher. That value proves the RCD can clear the L-E fault, but it tells the verifier very little about whether the installed L, N and CPC resistances resemble those assumed in the design.

    So I completely agree with your statement that testing should be against the design rather than simply against the tables.

    Perhaps the missing link is that the design should provide not only Max Zs, but also the relevant maximum phase-fault loop impedance/minimum phase-fault current where that is necessary to demonstrate the Chapter 43 calculation. Verification could then demonstrate that the physical circuit actually installed retains the characteristics upon which the design was based.

    That becomes particularly relevant as we move towards smarter protection such as solid-state circuit breakers. The better the protective device becomes at identifying and clearing faults independently of traditional fault-current magnitude, the less we can rely on successful protective-device operation as an indication that the circuit itself is electrically "good".

    For me the principle is becoming:

    Design demonstrates that the proposed circuit is safe. Verification should demonstrate that the circuit actually installed retains the electrical characteristics on which that safe design was based.

    And I think your point about neutral failures demonstrates that we may already have had a weakness in that design-to-verification link for a long time.

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